##################################################################################
#  (c) 2025 Vojtech Ters. All Rights Reserved.
#  Origin: https://iriscores.com
#  Contact: inquiry@iriscores.com
#
#  LICENSE:
#  This source code is provided freely for educational and commercial use,
#  provided that this header remains intact and the author (Vojtech Ters)
#  and origin (iriscores.com) are properly cited.
#
#  DISCLAIMER:
#  This code is provided "AS IS" without warranty of any kind. The author
#  assumes no liability for any damages arising from its use.
##################################################################################


###################################################
####### MAP Necessary 3rd Party Libraries  #######
# NOTE: DDR4 Requires Assertion licenses, its required to compile without assertions
# This is how to do it: config_compile_simlib -cfgopt {riviera.verilog.xpm:-na all}
# compile_simlib -simulator riviera 
#               -simulator_exec_path C:/Aldec/Riviera-PRO-2025.04-x64/bin 
#               -language all 
#               -no_systemc_compile 
#               -family kintexuplus 
#               -library all 
#               -directory C:/Users/vojta/Documents/GIT/iris-ip-cores/XilinxIPs/Vivado_2025_1_RivSimLib_2025_04_na
set IP_DIR "../../../XilinxIPs/Vivado_2025_2_RivSimLib_2025_04_na"
set DDR4_BASE "../../../XilinxIPs/"
set MODEL_BASE "./ALDEC_MODEL/"


#############################################################
####### Map Required 3rd-Party Arithmetics Libraries ########
amap xpm                        $IP_DIR/xpm
amap unisim                     $IP_DIR/unisim
amap unisims_ver                $IP_DIR/unisims_ver
amap unifast_ver                $IP_DIR/unifast_ver
amap unimacro_ver               $IP_DIR/unimacro_ver
amap secureip                   $IP_DIR/secureip
amap xilinx_vip                 $IP_DIR/xilinx_vip
amap microblaze_v11_0_16        $IP_DIR/microblaze_v11_0_16
amap proc_sys_reset_v5_0_17     $IP_DIR/proc_sys_reset_v5_0_17
amap lmb_v10_v3_0_16            $IP_DIR/lmb_v10_v3_0_16
amap lmb_bram_if_cntlr_v4_0_27  $IP_DIR/lmb_bram_if_cntlr_v4_0_27
amap blk_mem_gen_v8_4_12        $IP_DIR/blk_mem_gen_v8_4_12
amap iomodule_v3_1_13           $IP_DIR/iomodule_v3_1_13


###########################################
######  Setup Compilation Libraries #######
set COMPILE_LIBS "-l xpm \
          -l microblaze_v11_0_16 \
          -l xil_defaultlib \
          -l proc_sys_reset_v5_0_17 \
          -l lmb_v10_v3_0_16 \
          -l lmb_bram_if_cntlr_v4_0_27 \
          -l blk_mem_gen_v8_4_12 \
          -l iomodule_v3_1_13"

#############################################
######## Prepare Include Directories ########
set INCS "+incdir+${DDR4_BASE}DDR4_Custom/ip_1/rtl/map \ 
          +incdir+${DDR4_BASE}DDR4_Custom/rtl/ip_top \
          +incdir+${DDR4_BASE}DDR4_Custom/rtl/cal \
          +incdir+${MODEL_BASE}"

#########################################
###### Setup Simulation Libraries #######
set SIMULATION_LIBS "-L unisims_ver \
                     -L unimacro_ver \
                     -L secureip \
                     -L xpm \
                     -L microblaze_v11_0_16 \
                     -L xil_defaultlib \
                     -L work \
                     -L proc_sys_reset_v5_0_17 \
                     -L lmb_v10_v3_0_16 \
                     -L lmb_bram_if_cntlr_v4_0_27 \
                     -L blk_mem_gen_v8_4_12 \
                     -L iomodule_v3_1_13"

###########################################
####### Default Compilation Flags ########
set VHDL_FLAGS_COMMON "-incr -relax -nowarn COMP96_0594 -nowarn COMP96_0546 -nowarn ELBREAD_0056"
set SV_FLAGS_COMMON   "-incr -sv -na all +define+DDR4_8G_X16 +DEFINE+FIXED_1600 +DEFINE+ALLOW_JITTER"
set V_FLAGS_COMMON    "-incr -na all +define+DDR4_8G_X16 +DEFINE+FIXED_1600 +DEFINE+ALLOW_JITTER"
transcript off

#######################################
###### Concatenate Source Files #######
set worklist {}

#######################################
###### Aldec/Micron DDR4 Model ########
lappend worklist [list "${MODEL_BASE}arch_package.sv"   "work" ""];
lappend worklist [list "${MODEL_BASE}proj_package.sv"   "work" ""];
lappend worklist [list "${MODEL_BASE}ddr4_model.svp"    "work" ""];
lappend worklist [list "${MODEL_BASE}interface.sv"      "work" ""];
lappend worklist [list "Bidir_CrossConnect.v"           "work" ""];
lappend worklist [list "Micron_Model_Wrapper.sv"        "work" ""];

#################################
###### Block Design Files #######
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_0/sim/bd_629f_microblaze_I_0.vhd"      "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_1/sim/bd_629f_rst_0_0.vhd"             "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_2/sim/bd_629f_ilmb_0.vhd"              "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_3/sim/bd_629f_dlmb_0.vhd"              "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_4/sim/bd_629f_dlmb_cntlr_0.vhd"        "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_5/sim/bd_629f_ilmb_cntlr_0.vhd"        "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_6/sim/bd_629f_lmb_bram_I_0.v"          "xil_defaultlib" "-v2k5"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_7/sim/bd_629f_second_dlmb_cntlr_0.vhd" "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_8/sim/bd_629f_second_ilmb_cntlr_0.vhd" "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_9/sim/bd_629f_second_lmb_bram_I_0.v"   "xil_defaultlib" "-v2k5"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/ip/ip_10/sim/bd_629f_iomodule_0_0.vhd"       "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/bd_0/sim/bd_629f.vhd"                             "xil_defaultlib" "-93"];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_0/sim/DDR4_Custom_microblaze_mcs.vhd"          "xil_defaultlib" "-93"];

###########################################
####### Add AMD/Xilinx Base Global ########
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/phy/DDR4_Custom_phy_ddr4.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv"                    "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv"                          "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv"                       "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv"                            "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv"                       "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv"    "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv"  "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv"     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/ip_1/rtl/ip_top/DDR4_Custom_phy.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_wtr.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ref.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_rd_wr.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_periodic.sv"                      "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_group.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ecc_merge_enc.sv"                 "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ecc_gen.sv"                       "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ecc_fi_xor.sv"                    "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ecc_dec_fix.sv"                   "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ecc_buf.sv"                       "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ecc.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_ctl.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_cmd_mux_c.sv"                     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_cmd_mux_ap.sv"                    "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_arb_p.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_arb_mux_p.sv"                     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_arb_c.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_arb_a.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_act_timer.sv"                     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc_act_rank.sv"                      "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/controller/ddr4_v2_2_mc.sv"                               "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ui/ddr4_v2_2_ui_wr_data.sv"                               "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ui/ddr4_v2_2_ui_rd_data.sv"                               "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ui/ddr4_v2_2_ui_cmd.sv"                                   "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ui/ddr4_v2_2_ui.sv"                                       "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/clocking/ddr4_v2_2_infrastructure.sv"                     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_write.sv"                               "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_wr_byte.sv"                             "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_wr_bit.sv"                              "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_sync.sv"                                "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_read.sv"                                "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_rd_en.sv"                               "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_pi.sv"                                  "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_mc_odt.sv"                              "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv"                    "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_cplx_data.sv"                           "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_cplx.sv"                                "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_config_rom.sv"                          "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_addr_decode.sv"                         "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_top.sv"                                 "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv"                        "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_cal.sv"                                     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv"                    "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/ddr4_v2_2_dp_AB9.sv"                                  "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ip_top/DDR4_Custom_ddr4.sv"                               "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ip_top/DDR4_Custom_ddr4_mem_intfc.sv"                     "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/cal/DDR4_Custom_ddr4_cal_riu.sv"                          "xil_defaultlib" ""];
lappend worklist [list "${DDR4_BASE}DDR4_Custom/rtl/ip_top/DDR4_Custom.sv"                                    "xil_defaultlib" ""];

lappend worklist [list "C:/AMDDesignTools/2025.2/data/verilog/src/glbl.v"  "xil_defaultlib" ""];
lappend worklist [list "UI_TPG.vhd"                                       "work" "-2008"];
lappend worklist [list "PG150_TB.sv"                                      "work" ""];
transcript on

alib riviera/work
alib riviera/xil_defaultlib
foreach entry $worklist {
    #########################################
    # Extract File And Compilation Options: 
    # Index 0 = File
    # Index 1 = Destination Library
    # Index 2 = Compilation Options
    set file        [lindex $entry 0]
    set target_lib  [lindex $entry 1]
    set file_opts   [lindex $entry 2]

    #############################################################
    if [regexp {\.vhdl?$} $file] { ###### VHDL Compilation ######
    #############################################################
        
        acom {*}$VHDL_FLAGS_COMMON {*}$file_opts -work {*}$target_lib $file

    ###################################################################################
    } elseif [regexp {\.(sv|svp)?$} $file] { ####### System Verilog Compilation #######
    ###################################################################################
        
        alog {*}$COMPILE_LIBS {*}$INCS {*}$SV_FLAGS_COMMON {*}$file_opts -work {*}$target_lib $file

    ######################################################################################
    } elseif [regexp {\.(v|vp|vh)?$} $file] { ####### Standard Verilog Compilation #######
    ######################################################################################
        
        alog {*}$COMPILE_LIBS {*}$INCS {*}$V_FLAGS_COMMON {*}$file_opts -work {*}$target_lib $file

    } else {
        error "Unsupported compilation file type: $file"
    }
}

###############################
####### Setup TP-Level ########
set top_level work.PG150_TB

#####################################################
####### ####### Launch the simulation ####### #######
asim +access +r {*}$SIMULATION_LIBS -O5 xil_defaultlib.glbl $top_level -t 1ps

#############################################
####### Add Custom Wave Configuration #######
do wave_pg150.do

###################################
####### Run the simulation ########
# NOTE: "endsim" causes the Wave / Object Windows to fail to add more signals.
run 8us
set SimTime [simstats time]
echo "Final Simulation Time: $SimTime"