Custom IP Solutions for FPGA & ASIC designs
Why you should consider my design services?
- Proven 8+ years of history & expertise in FPGA & digital design (Aerospace, Data Center and Measurement equipment)
- Specialized in video, image and generic complex digital signal processing techniques (Scaling, Buffering,Transforms,Filtering …)
- Proficient in optimizing designs for performance by pipelining and parallel processing
- In-depth understanding and practical experience of various interface protocols (AXI, PCIe, AHB, I2C, SPI …)
- Proven ability to resolve tight timing closure issues in STA and mitigate CDC and reset-related design issues
- Capacity to define and optimize hardware/software interfaces for efficient low-level driver development
- Adheres to best practices for VHDL coding, employing modular design principles and reusable IP components
- Primarily using VHDL 2008 language to mitigate issues that similar languages present
- Knowledge of building tailored verification test-benches to properly test and verify complex designs
- Expert knowledge of AMD/Xilinx tools (Vivado / Vitis / Petalinux) and devices (7-Series / Ultrasclae+ / SoC / MpSOC)
- Knowledge of various verification tools – Questa / Questa CDC / Questa VIP and Aldec’s Riviera PRO
- Willingness to tackle various challenging issues, tasks and design problems
After graduating from Czech Technical University in Prague, CZ, in 2016, I started working as a software enginner for acceleration of computing-intensive algorithms for signal and image processing in nVidia CUDA technology. Soon after, I started my career as an FPGA designer and since then, I have widely broadened my expertise and knowledge in regards to FPGAs and digital design. After working for several companies over the years, I have finally decided to work as a freelance engineer.
I believe that true power comes from the knowledge and freedom – that’s why I prefer to code the necessary components from ground up to the software. This allows me to balance and decide which parts of the algorithms are favored to be software implemented, which parts are rather suited for the FPGA and high-speed processing and where I am allowed to make simplifications as necessary to save both time and resources. I have successfully written several Linux Kernel drivers, though I am not primarily linux-kernel oriented.
I have a wide area of expertise in FPGA design and AMD FPGAs in general, though I do not hesitate to say that I do eventually lack an experience or two (Namely no experience with AI or networking for example.). I have encountered a lot of IPs and code written by “Professional FPGA Engineers“. I am not like any of them. My goal is to write clean and well-maintainable code base that is easy to verify and pleasure to read. Most of my IPs are highly confgurable, written in modern VHDL 2008 standard and include custom Test-Benches, scripts and eventually sample drivers or other support materials. To further emphasize my commitment in professional digital RTL design, I began utilizing a leading commercial RTL Simulator (Aldec’s Riviera PRO) for thorough IP verification and to guarantee a fully tested code deliverables.