AMD FPGA Design Debugging
A practical guide to debugging and initial bring-up for AMD FPGAs. Master the seamless transition from simple VIO probes to a complex AXI infrastructure with an embedded MicroBlaze processor.
Simulating DDR4 Ecosystem with Aldec’s Riviera-Pro
Let’s be honest: for those who believe it is necessary to use a full-featured soft-core memory controller connected to an industry-standard DDR4 memory model—no, it doesn’t have to get that complicated. In fact, I would highly suggest finding a more straightforward...
Video Synchronization options in FPGA
Video Synchronization options in FPGA When dealing with live video, especially in FPGAs or ASICs, you’ll inevitably encounter synchronization challenges. These can range from simple refresh rate conversions and multi-stream synchronization to video alignment...
HDL Simulator Comparison
HDL Simulator Comparison Sooner or later, every HDL digital engineer considers the usage of a different HDL simulator for a varienty of reasons (Compatibility, Speed, Additional Options, Language Support, Platform Support etc.). I will skip the obvious introduction of...
PCIe MSI Interrupt latency on x86
PCIe MSI Interrupt latency on x86 I have been using MSI / MSI-X interrupts for quite some time for my FPGA-Based designs with plenty of various DMAs. They have been serving well over the years and I have never encountered any errors except for rare cases where I...