Offline analysis of DSP components during RTL-based simulations

Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks, Filters, FFTs and other parts of some complex signal processing IPs. Checking whether they work as intended and that the DSP block doesn’t create any signal artifacts such as underflows or overflows. For this purpose, the Mathwork’s simulink block could be used as its a great tool for simulation as well (One can compile the simulink model into an IP as well). But what if we have some complex RTL- based IP, that’s needs to be verified by some long data sequence?

In that case, it might not be a bad idea to create this sequence somewhere outside the simulator, save it to a .txt, feed the IP with these data and then save the results back to a .txt for further processing, for example, Matlab , Octave, Python or C/C++ would do just fine. One should however has to take extra care, if the data in the .txt file are representable in the testbench, which uses these data. Eg. one of my mistakes was to use 32768 in 2’S complement format Q16.15 (Where the maximum is defined as 0x7FFF → 32767). For sure, directly interacting with the simulator would also be great, but as far as I know, there is no simple way how to do that at least for VHDL.

use STD.textio.all;
use ieee.std_logic_textio.all;

-----------------------------
------- Data Generator ------
process(Clk)
  file F_TB_Data_I         : text open read_mode is "TB_Data_I.txt";
  file F_TB_Data_Q         : text open read_mode is "TB_Data_Q.txt";
  variable V_TB_Data_Q     : line;
  variable V_TB_Data_I     : line;
  variable Int_I           : integer;
  variable Int_Q           : integer;
begin
    if rising_edge(Clk) then
        readline(F_TB_Data_I,V_TB_Data_I);
        readline(F_TB_Data_Q,V_TB_Data_Q);
        read(V_TB_Data_I, Int_I);
        read(V_TB_Data_Q, Int_Q);
        Time_Data_I <= std_logic_vector(to_signed(Int_I,16));
        Time_Data_Q <= std_logic_vector(to_signed(Int_Q,16));
    end if;
end process;

--------------------------------------------------------
-------- SAVE DATA TO TXT FILE USING VHDL TEXTIO -------
process(Clk)
file F_FFT_Data_I     : text open write_mode is "FFT_Data_I.txt";
file F_FFT_Data_Q     : text open write_mode is "FFT_Data_Q.txt";
variable V_Data_Q     : line;
variable V_Data_I     : line;
begin
    if rising_edge(Clk) then
        if FFT_Data_Vld = '1' then
            write(V_Data_Q,to_integer(signed(FFT_Data_Q)));
            write(V_Data_I,to_integer(signed(FFT_Data_I)));
            writeline(F_FFT_Data_I, V_Data_I);
            writeline(F_FFT_Data_Q, V_Data_Q);
        end if;
    end if;
end process;

Tip: Saved data may be loaded to Matlab via “load(‘filename.txt’)“.
Tip: Data sequence may be generated by “printf(“%d\n”)“

DSP IP Simulation