Custom IP Solutions for FPGA & ASIC designs
- Proven 8+ years of history & expertise in FPGA & digital design (Aerospace, Data Center and Measurement equipment)
- Specialized in video, image and generic complex digital signal processing techniques (Scaling, Buffering,Transforms,Filtering …)
- Proficient in optimizing designs for performance by pipelining and parallel processing
- In-depth understanding and practical experience of various interface protocols (AXI, PCIe, AHB, I2C, SPI …)
- Proven ability to resolve tight timing closure issues in STA and mitigate CDC and reset-related design issues
- Capacity to define and optimize hardware/software interfaces for efficient low-level driver development
- Adheres to best practices for VHDL coding, employing modular design principles and reusable IP components
- Primarily using VHDL 2008 language to mitigate issues that similar languages present
- Knowledge of building tailored verification test-benches to properly test and verify complex designs
- Expert knowledge of AMD/Xilinx tools (Vivado / Vitis / Petalinux) and devices (7-Series / Ultrasclae+ / SoC / MpSOC)
- Knowledge of various verification tools – Questa / Questa CDC / Questa VIP and Aldec’s Riviera PRO
- Willingness to tackle various challenging issues, tasks and design problems
ll available IPs are eligible for a free evaluation in an industry-standard EDA simulator selected by the user, with no inherent limitations (unless otherwise specified). Hardware testing is also available free-of-charge. However, all hardware evaluation configurations will include a time-limited mechanism (typically several hours) that requires a device reset to continue operating as intended. All IPs are delivered as encrypted RTL source code by default. Unencrypted RTL source code is available for purchase, as are various licensing options; please contact me for all pricing and details.
After graduating from Czech Technical University in Prague in 2016, I began my career as a Software Engineer focused on accelerating computing-intensive algorithms using nVidia CUDA technology. I soon transitioned to FPGA Design, where I have since significantly broadened my expertise in digital design and high-speed processing. After several years in corporate roles, I decided to become a freelance engineer to maximize my impact and freedom.
My professional strength lies in architecting efficient hardware-software co-design. I prefer to build components from the ground up, allowing me to precisely balance the workload: deciding which parts of an algorithm are best suited for software and which require the speed of an FPGA. I have experience writing Linux Kernel drivers and possess deep expertise in FPGA design, particularly with AMD (formerly Xilinx) devices.
I prioritize clean, well-maintainable, and verifiable code over simply shipping an IP.
My goal is to write code that is a pleasure to read. To ensure the highest professional standards:
Most of my Intellectual Property (IP) is highly configurable, written in modern VHDL 2008.
All deliverables include custom Test-Benches, scripts, and support materials (e.g., sample drivers).
I utilize a leading commercial RTL Simulator, Aldec’s Riviera PRO, for thorough verification to guarantee a fully tested code base.