The FFT IP Implements by default the Cooley-Tukey Decimation in Frequency (DIF) FFT Algorithm, an efficient and performance-optimized implementation of the DFT (Discrete Fourier Transform) with sizes of up to 65536 samples. The core support both fixed point and floating point (Single Precision) implementation, floating point math however requires the usage of external IPs. Both forward and Inverse transforms are supported. The core can be also reconfigured during runtime and provides various status signals – including invalid FFT packet detection and Math overflow problems. The IP supports both Base-Radix and Pipelined architectures for maximum performance. Base-radix allows for computing of 1 FFT butterfly (Either Radix 2 / Radix 4 or Radix 8) per clock cycle. Pipelined architecture allows for computing with the same speed in all FFT stages in parallel (IE Fully Pipelined at a cost of extra resources). Mixed radix tranforms are also supported. The core has standardized AXI4-Lite status & control interface with Optional CDC to facilitate asynchronous control and processing clock domains.

Base radix IP configuration (R2 / R4 or R8) implements a  single FFT stage. In order to process the required transform, multiple stage loops are required. Amount of FFT stages is equal to ceil(log(Radix,FFT size)), IE. for a 4096-point transform and base radix of 4, 6 stages needs to be processed. Amount of stages required to compute the transform directly relates to the the core’s latency.Thats why higher Base-R transforms reduce latency and increase the overall performance of the core. The difference between base-R and pipeline architecture is that within the pipeline architecture, multiple transforms are processed in parallel – although Base-R and pipelined architecture will still have the same latency (Considering the base radix is equal). The core also supports both Decimation in Frequency (DIF) and Decimation in Time (DIT). There are however no benefits of using DIT over DIF and thus the results will be equal in both cases except for some rounding errors due to different order of math applied.

NOTE: The IP’s resource estimates and FMAX timing performance were evaluated with Vivado 2024.2 tool targetting xcku5p-ffvb676-2-e device (KCU116 – Kintex Ultrascale+) or xcu50-fsvh2104-2-e (Alveo U50 – Virtex Ultrascale+). All evaluation was done with the default tool configuration for Synthesis / Optimization / Place & Route. Due to the excessive amount of possible IP configuration, the assumed “worst-case” was processed only with 32-bit data with and 24-bit twiddle width. Fixed Point DIF architecture. Mixed radix implementations would require additional DSPs. The available optional timing optimizations within the core were also enabled in all cases.