FFT IP Overview The FFT IP Implements by default the Cooley-Tukey Decimation in Frequency (DIF) FFT Algorithm, an efficient and performance-optimized implementation of the DFT (Discrete Fourier Transform) with sizes of up to 65536 samples. The core support both fixed...
AXI Interconnect IP Overview The AXI4 Interconnect IP provides a performance-optimized generic communication AXI4 crossbar switch between multiple Slave and Master interfaces (M-to-N). There is a dedicated crossbar for both AXI4-read and AXI4-write channels. Generic...
AXI DMA IP Overview AXI DMA IP implements a generic data-mover engines on AXI4 protocol. Written from ground up in VHDL2008 standard and verified in simulator and on KCU116 hardware. It is available as a standadalone simple DMA engine (Also known as direct register...
Video Mixer IP Overview The Video Blender/Mixer IP is a highly-configurable full-featured multi-channel video mixer. It supports generic amount AXI-compliant video stream channels, which can be arbitrary repositioned, cropped, chroma-keyed and/or blended together on a...
Video Buffer IP Overview The Video Buffer IP provides capability to buffer video frames inside external DDR memory. It is specifically designed around AMD’s Memory interface IP (PG150) and its UI memory interface. It is fully designed and verified in modern...
