HDL Simulator Comparison Sooner or later, every HDL digital engineer considers the usage of a different HDL simulator for a varienty of reasons (Compatibility, Speed, Additional Options, Language Support, Platform Support etc.). I will skip the obvious introduction of...
PCIe MSI Interrupt latency on x86 I have been using MSI / MSI-X interrupts for quite some time for my FPGA-Based designs with plenty of various DMAs. They have been serving well over the years and I have never encountered any errors except for rare cases where I...
HDMI 1080p Video with KCU116 In order to showcase some of my self-developed IPs dedicated for video processing, I had to choose a proper development platform, that would allow me to quickly prototype and present results (IE reduce time to market). Because the only...
QSPI Flash Simulation As the title of the post suggests, my intention was to originally write about QSPI (Quad SPI) only, but I would not have likely written about it when everything worked as intended, but as we already know, things are never that simple and the...
The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and...
This time, I have decided to create a small and simple demo in order to show how to simulate PCIe interface (Without any DMA or PCIe bridge) for Xilinx devices as the PCIe is slowly becoming a standardized interface for FPGA in most applications from consumer...
