Video Buffer

by | Mar 19, 2024

IP Overview

The Video Buffer IP provides capability to buffer video frames inside external DDR memory. It is specifically designed around AMD’s Memory interface IP (PG150) and its UI memory interface.  It is fully designed and verified in modern VHDL2008 except for asynchronous FIFOs, which are at this time implemented through vendor’s macros. Amount of video channels is configurable through generics. The IP even supports auxiliary communication channel for 3-rd party IPs to/from the DDR memory. Amount of video buffers per channel is by default 3  to ensure the fastest response time and reduce the frame latency to a minimum. All data reception and transmission ports are AXI video stream compliant and various status and report signals are available on a per-channel / per-buffer basis, including the detection of a stalled video channel (A video channel where no new data are being received).  In order to further maximize efficiency of the transfers, all transaction heading to or from the memory interface are bursted (Except for a singular case in order to be able to receive just one frame over a larger period of time). The UI burst size also follows the original Xilinx’s moto “Everything Programmable”.

The IP is intended to be used with the Video Mixer IP and/or other video processing pipelines such as video scalers and/or video croppers. Any application, that basically involves “data framing” is however suitable. In order to further meet high performance requirements (Especially in terms of memory Bandwidth), arbitrary UI interface width is supported as well as arbitrary pixel size. Naturally, S_AXI and M_AXI interface ports support external asynchronous clocking and up to 1 pixel per clock cycle.

For more information, please visit the Video Mixer IP demo, which utilizes this IP within the KCU116 development platform.
Detailed documentation is available upon request, please contact me for more details!